Nowadays, many electrical appliances are widely used with personal computers due to the amazing power of the personal computers. With the processing speed of the personal computer is increased, the bus transmission interface used with the personal computer has a high transmission speed. An example of the bus transmission interface includes a universal serial bus (USB), a PCI Express (PCIe) interface, a serial advanced technology attachment (SATA) bus, and the like. For achieving optimum impedance match of the transmission line, a termination resistor is usually mounted on the high speed transceiver of the high-speed bus transmission interface to avoid the return loss resulting from the mismatch. As a consequence, the problem of causing distorted signals upon transmission is overcome.
Conventionally, the off-chip termination resistor can meet the above requirements of the transceiver. However, the cost and the reliability of the off-chip termination resistor are not satisfactory. Recently, on account of cost-effectiveness and reliability, an embedded chip which is also called system on chip (SOC) is developed. Consequently, an on-chip termination resistor is also developed.
Referring to FIG. 1, a schematic circuit diagram of a chip having an on-chip termination resistor implemented by an analog adjustment technology is illustrated. As shown in FIG. 1, a metal-oxide-semiconductor (MOS) transistor 10, an operational amplifier 11 and a voltage divider 12 are mounted on the chip 1. The MOS transistor 10 is served as the on-chip termination resistor (Rmos). An external resistor Rext is also electrically connected to the chip 1. By regulation of the operational amplifier 11 and the voltage divider 12, the relation between the resistance Rext of the external resistor and the resistance Rmos of the MOS transistor 10 is deduced as: Rext/Rmos=2R/R. For example, if the resistance Rext of the external resistor is 100 ohms, the resistance Rmos of the MOS transistor 10 is 50 ohms.
Since the voltage Vds across the source and the drain of the MOS transistor 10 is varied during data transmission of the transceiver, the resistance Rmos of the MOS transistor 10 is non-linear. In addition, using the additional external resistor Rext as the reference resistance increases extra cost.
Referring to FIG. 2, a schematic circuit diagram of a chip having an on-chip termination resistor implemented by a digital adjustment technology is illustrated. The chip 2 includes a transistor-resistor array 20, an internal current source 21, a reference voltage source Vref, two low pass filters 220, 221, a comparator 22, a digital code generator 23 and a register 24. A digital code generated from the digital code generator 23 is temporarily stored in the register 24. The resistance R of the transistor-resistor array 20 is determined according to the digital code stored in the register 24. Since a constant current I is outputted from the internal current source 21, the voltage V across the transistor-resistor array 20 is proportional to the resistance R of the transistor-resistor array 20, i.e. V=I×R. Accordingly, the voltage V across the transistor-resistor array 20 is varied with the digital code. The transistor-resistor array 20 and the reference voltage source Vref are electrically connected to the low pass filters 220 and 221, respectively, for filtering off the high-frequency components but retaining the low-frequency components. When the computer system is started to execute the self-examination operation, a plurality of digital codes in an ascending order are successively generated and transmitted from the digital code generator 23 to the register 24. As a consequence, the voltage V across the transistor-resistor array 20 is gradually increased until the potentials of the input terminals of the comparator 22 are equal, i.e. V=Vref. Meanwhile, the digital code stored in the register 24 denotes an optimum digital code. According to this optimum digital code, the resistance values of other transistor-resistor arrays (not shown) of the computer system can be determined.
As known, for implementing the digital adjustment, the reference voltage source Vref and the internal current source 21 should be stable and reliable. Generally, since the internal current source 21 has a variation from +/−25% to +/−30%, the resistance R of the transistor-resistor array 20 also has a variation from +/−25% to +/−30%. That is, the stability and the reliability of the internal current source 21 are not satisfactory. Moreover, the trend of designing the chip is toward low power consumption. Due to the consumption of the constant current I, the digital adjustment of FIG. 2 consumes much power.